The present invention relates to a fabrication method for an integrated circuit. More particularly, the present invention relates to a fabrication method for forming a semiconductor structure with high-voltage sustaining capability.
In current integrated circuit processing, controllers, memories, circuits of low-voltage operation and power devices of high-voltage (HV) operation are largely integrated into a single chip to achieve a single-chip system. The power device, such as VDMOS, IGBT and LDMOS, is employed to increase power switching efficiency and decrease the loss of energy resources.
Moreover, many currently available power devices use both NMOS and PMOS high-voltage transistors (hereinafter referred to as HV transistors). In order to achieve HV transistors with a channel length of less than 0.5 μm, by a conventional manufacturing process, it is necessary to appropriately increase the doping of the substrate so as to prevent defects, such as punch-through of undesired electrical connections between two regions having different potentials during operation under high bias and working voltages.
Hence, there is a need for an HV device that can better sustain high-voltage operation and meet the demand of size reduction.
Two different kinds of HV MOS devices are disclosed in U.S. Pat. No. 6,455,893 and U.S. Pat. No. 6,277,675. In U.S. Pat. No. 6,455,893, Gehrmann et. al. disclose a HV PMOS with a drain extension region produced by means of the use for logic MOS transistors. In U.S. Pat. No. 6,277,675, Tung teaches a method of fabricating a high voltage (HV) MOS device on a substrate with an N-type well region and a P-type well region thereon. The method disclosed in U.S. Pat. No. 6,277,675 can control the channel length of the HV MOS device and a higher voltage can be applied to the device without causing electrical breakdown resulting in device damage.